Semiconductor integrated circuit devices are designed using various computer aided means to produce a logical circuit in which various functional elements are identified and interconnected to form particular logic functions. Computer-aided design (CAD) or other design tools are typically used to generate lithography data based on the design and the lithography data is used to form a photomask set that is used in the actual fabrication of the semiconductor integrated circuit (IC) devices.
A standard cell type semiconductor IC device is an application specific integrated circuit (ASIC) device designed using multiple standard cells. Each standard cell may include a group of transistor and interconnect structures that provide a boolean logic function (e.g., AND, OR, XOR, XNOR, invertors) or a storage function (flipflop or latch, for example). In a standard cell system, the standard cells are advantageously maintained in a library and various integrated circuit devices can be designed by selecting desired standard cells from the library and combining them in various arrangements to form a most suitable cell arrangement pattern that forms part of the layout of the integrated circuit device.
The design process for standard cell semiconductor IC devices includes constructing the integrated circuit design out of the selected standard cells that are connected together electrically, i.e. routed, using wire interconnects which are also used to route the cells to input and output terminals. The standard cells and connections between them may be stored in databases called “netlists” (i.e., lists of symbolic interconnections). The netlist describes the connectivity of the standard cells within the semiconductor IC device design. One or more computer-aided design (CAD) tools may be used to generate the netlist of the selected standard cells and the interconnections between the cells and input/output. The netlist may be used by a floor planner, placement tool, or other design tool, to place the selected cells at particular locations in the layout of a standard cell integrated circuit device.
The design of the standard cell semiconductor IC device may be carried out by an APR (automatic placement and routing) design tool that includes a placer and a router, by selecting standard cells from the library of standard cells and placing and routing the cells according to design instructions provided to the APR tool such as in the netlist. The placer determines the optimum location of each standard cell of the integrated circuit on the semiconductor substrate, and the router optimizes the routing of input/output lines and the connection between standard cells so that the integrated circuit layout does not become overly congested by input/output and other routing lines. Other CAD tools are also available and may be used in the design of standard cell semiconductor IC devices.
In addition to the standard cells that may be selected from a library, the device design may include other standard cells such as user specified target cells with different operational characteristics. When such target cells are used along with the standard cells from the library to form a standard cell semiconductor IC device, additional challenges in the placement and routing of the cells is imposed. Target cells that operate at higher power consumption levels, for example, require the routing wires used to couple the target cells to ground and power sources, to operate at high power levels and carrying high currents. As such, these wires are especially susceptible to electromigration (EM) failure and even complete blowout of the wire, thus representing a significant shortcoming of conventional technology.